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1 for more information www.linear.com/lt8603 typical application features description 42v, low i q , quad output triple monolithic buck converter and boost controller the lt ? 8603 is a highly flexible, quad output regulator combining two high input voltage capable monolithic step-down switching regulators, one low input voltage capable monolithic step-down regulator, and a boost controller to satisfy a wide range of applications while occupying minimal board space. with the boost controller configured to supply the chip v in supply, the lt8603 produces three precisely regulated outputs even when the boost input voltage falls signifi - cantly below the regulated output voltages, such as dur - ing an automotive cold crank scenario. alternatively, with the boost controller driven from one of the step-down regulator outputs or configured as a sepic, the lt8603 provides four precisely regulated outputs over a wide input voltage?range. the lt8603 provides robust regulation by including a cycle-by-cycle current limit for all step-down regulators, thermal shutdown, and a boost controller that can tolerate reverse battery connections and negative transient input voltages down to C42v. cold crank tolerant automotive triple output supply applications n flexible power supply system capable of four regulated outputs with v batt << v out n two high voltage synchronous buck regulators n 3v to 42v input voltage range n output currents up to 2.5a and 1.5a n one low voltage synchronous buck regulator n 2.6v to 5.5v input voltage range n output currents up to 1.8a n one boost controller allows buck converters to regulate with v b att << v out n selectable burst mode ? operation allows low 28a i q with high voltage channels active n programmable power-on reset n individual channel power good indicators n step-down switching frequency: 250khz to 2.2mhz n available in 40-lead qfn (6mm 6mm) package n automotive stop-start and cold?crank ride through n last-gasp cpu power hold-up n industrial controls and power supplies all registered trademarks and trademarks are the property of their respective owners. lt8603 response to a cold crank automotive input waveform 8603 0 8 8 3 8603 rst reset 3 8 3 3 33 3 3 3 v batt v out4 v out1 v out2 v out3 lt8603 8603f time (10ms/div) voltage 2v/div 0v 8603 ta01b
2 for more information www.linear.com/lt8603 pin configuration absolute maximum ratings supply voltages v in , pv i n1 ,2 ............................................ C 0. 3v to 42v pv i n3 ....................................................... C 0. 3v to 6v en/uvlo .................................................................. 42v is p4 , is n4 .................................................. C 42v to 42v trks s1 -2, ru n3 , fb4 , p g1 -4, sync ......................... 6v fse l4 a, fse l4 b, rst ................................................. 6v fb1 -3, cpor, poren ............................................... 3.6v bias ........................................................... C 0.3v to 15v operating junction temperature (notes 2, 5) lt8603 e ............................................ C 40 c to 125 c lt8603 i ............................................. C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (note 1) 3 0 38 3 36 3 3 33 3 3 0 3 0 6 rst 30 0 ja = 33c/w, jc = 2c/w exposed pad (pin 41) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt8603euj#pbf lt8603euj#trpbf lt8603uj 40-lead (6mm 6mm) plastic qfn C40c to 125c lt8603iuj#pbf lt8603iuj#trpbf lt8603uj 40-lead (6mm 6mm) plastic qfn C40c to 125c consult adi marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping?container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. http://www.linear.com/product/lt8603#orderinfo lt8603 8603f
3 for more information www.linear.com/lt8603 electrical characteristics parameter conditions min typ max units bias and internal regulators minimum operating v in for channels 1, 2 and 3 l 2.7 3.0 v minimum v in to start for channels 1, 2 and 3 l 3.1 3.3 v minimum operating v in for channel 4 l 3.0 3.2 v minimum v in to start for channel 4 l 4.0 4.15 v v in quiescent current, shutdown v bias = 0v, en/uvlo = 0.4v 0.1 1 a total operating current v batt v batt = 12v, channels 1 and 2 active, no-load (note 4) v batt = 12v, all channels active, no-load (note 4) 28 50 a a en/uvlo threshold en/uvlo rising l 1.15 1.2 1.25 v en/uvlo falling l 1.1 1.15 1.2 v en/uvlo input current en/uvlo = 1.2v C50 50 na intv cc4 regulated voltage v bias = 0v v bias = 6v l l 4.4 4.7 4.6 5 4.8 5.2 v v int v cc4 regulator load regulation intv cc4 at 1ma C intv cc4 at 40ma 70 mv oscillator switching frequency r t = 28.7k r t = 243k l l 1.8 0.224 2 0.25 2.2 0.284 mhz mhz sync input frequency range l 0.25 2.2 mhz sync input voltage low l 0.3 v sync input voltage high l 1.2 v sync input current C100 100 na fsel4a, fsel4b input voltage low l 0.4 v fsel4a, fsel4b input voltage high l 2 v fsel4a, fsel4b input current l C100 100 na channel 1 feedback voltage fb1 l 0.985 1 1.015 v input current fb1 l C100 100 na fb1 line regulation v in = 3v to 42v 0.002 0.01 %/v sw1 peak current limit (note 3) 2.0 2.7 3.7 a sw1 leakage current 0.1 1 a sw1 top on-resistance i sw1 = 1a 240 m sw1 bottom on-resistance i sw1 = 1a 170 m lower fb1 power good threshold percentage of v fb1 , v fb1 falling l 89 92 95 % upper fb1 power good threshold percentage of v fb1 , v fb1 rising l 104 107 110 % power good threshold hysteresis 0.8 % pg1 output voltage low i pg1 = 350a l 0.13 0.3 v pg1 leakage current pg1 = 5v, fb1 = 1v l 6 a trkss1 pull-up current trkss1 = 0.2v 1.5 2.4 3.1 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, en/uvlo = 3v unless otherwise?noted. (note 2) lt8603 8603f
4 for more information www.linear.com/lt8603 electrical characteristics parameter conditions min typ max units channel 2 feedback voltage fb2 l 0.985 1 1.015 v input current fb2 l C100 100 na fb2 line regulation v in = 3v to 42v 0.002 0.01 %/v sw2 peak current limit (note 3) 3.2 4.0 5.3 a sw2 leakage current 0.1 1 a sw2 top on-resistance i sw2 = 1a 150 m sw2 bottom on-resistance i sw2 = 1a 100 m lower fb2 power good threshold percentage of v fb2 , v fb2 falling l 89 92 95 % upper fb2 power good threshold percentage of v fb2 , v fb2 rising l 104 107 110 % power good threshold hysteresis 0.8 % pg2 output voltage low i pg2 = 350a l 0.13 0.3 v pg2 leakage current pg2 = 5v, fb2 = 1v l 6 a trkss2 pull-up current trkss2 = 0.2v 1.5 2.4 3.1 a channel 3 pv in3 operating voltage pv in3 falling l 2.6 5.5 v pv in3 undervoltage lockout pv in3 falling l 2.35 2.6 v feedback voltage fb3 l 788 800 812 mv fb3 line regulation v in = 3v to 42v 0.002 0.01 %/v input current fb3 l C100 100 na sw3 leakage current 0.1 1 a sw3 peak current limit (note 3) 2.6 3.2 3.8 a sw3 pmos on-resistance i sw3 = 1a 150 m sw3 nmos on-resistance i sw3 = 1a 100 m lower fb3 power good threshold percentage of v fb3 , v fb3 falling l 89 92 95 % upper fb3 power good threshold percentage of v fb3 , v fb3 rising l 104 107 110 % power good threshold hysteresis 0.2 % pg3 output voltage low i pg3 = 350a l 0.13 0.3 v pg3 leakage current pg3 = 5v, fb3 = 0.8v l 6 a run3 threshold voltage l 1.15 1.20 1.25 v run3 input current C100 100 na soft-start time 0.7 1 1.3 ms the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, en/uvlo = 3v unless otherwise?noted. (note 2) lt8603 8603f
5 for more information www.linear.com/lt8603 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt8603e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt8603i is guaranteed to meet performance specifications from C40c to 125c junction temperature. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures above 125c. parameter conditions min typ max units channel 4 feedback voltage fb4 l 788 800 812 mv fb4 line regulation v in = 3.2v to 42v 0.002 0.01 %/v input current fb4 l C100 100 na soft-start time 1 ms current comparator limit threshold v isp4 to v isn4 , v cm = 2v to 42v l 43 50 57 mv current comparator input common mode range 2 42 v isp4, isn4 input currents, sleep v isp4 = v isn4 = 2v to 42v, fb4 = 1v, sync = 0v 200 na isp4, isn4 input currents, active v isp4 = v isn4 = 2v to 42v, fb4 = 0v, sync = 0v 34 44 a isp4, isn4 input currents v isp4 = v isn4 = C42v 7 10 ma gat e4 high side pmos on-resistance 2.5 gat e4 low side nmos on-resistance 1.25 fb4 power good threshold percentage of v fb4 , v fb4 falling l 89 92 95 % power good threshold hysteresis 0.2 % pg4 output voltage low i pg4 = 350a l 0.13 0.3 v pg4 leakage current pg4 = 5v, fb4 = 0.8v l 6 a power-on reset por delay time cpor = 1000pf l 31 35.2 39.4 ms rst output voltage low i rst = 100a l 0.1 0.2 v rst pull-up current por timed out, rst = 0v 20 a rst leakage current por timed out, rst = 6v C100 100 na poren threshold l 1.15 1.2 1.25 v poren pull-up current poren = 0v 0.6 1.0 1.4 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, en/uvlo = 3v unless otherwise?noted. (note 2) note 3: current limit is assured by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycles. note 4: measurement made using the circuit titled, details of front page application in the typical applications section. note 5: this ic includes overtemperature protection that is intended to protect the device during overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum junction temperature will reduce?lifetime. lt8603 8603f
6 for more information www.linear.com/lt8603 typical performance characteristics channel 1 efficiency vs load v out1 = 5v, f sw = 2mhz channel 2 efficiency vs load v out2 = 3.3v, f sw = 2mhz channel 3 efficiency vs load v out3 = 1.2v, f sw = 2mhz channel 4 efficiency vs load v out4 = 8v, f sw = 1mhz channel 4 efficiency vs load v out4 = 8v, f sw = 1.0mhz no-load i (v in ) vs v in all channels enabled (note 4) channel 1 efficiency vs load v out1 = 5v, f sw = 1mhz channel 2 efficiency vs load v out2 = 3.3v, f sw = 1mhz channel 3 efficiency vs load v out3 = 1.2v, f sw = 1mhz t a = 25c, v in = pv in1 = pv in2 = 12v, en/uvlo = 3v and pv in3 = 3.3v unless otherwise noted. lt8603 8603f 20 0.01 0.1 1 3 0 10 20 30 40 50 30 60 70 80 90 100 efficiency (%) v out2 = 3.3v, f sw = 2mhz 8603 g05 pv in2 = 12v pv in2 = 24v 40 burst mode operation load current (a) 0.001 0.01 0.1 1 2 0 10 20 50 30 40 50 60 70 80 90 100 efficiency (%) out3 sw 60 8603 g06 pv in3 = 2.6v pv in3 = 3.3v pv in3 = 5.5v burst mode operation light load burst r sense = 4.0m l4 = 1.5h v batt 6v 70 4.5v 3v load current (a) 0.001 0.01 0.1 0 10 20 30 80 40 50 60 70 80 90 100 efficiency (%) out4 sw 8603 g07 90 burst mode operation r sense = 4.0m l4 = 1.5h v batt 6v 4.5v 3v 100 load current (a) 0.0 0.8 1.5 2.3 3.0 0 10 20 30 efficiency (%) 40 50 60 70 80 90 100 efficiency (%) v out4 load current (a) out1 sw = 8v, f sw = 400khz 8603 g08 v batt (v) 0 10 20 30 40 8603 g01 50 0 50 100 150 200 250 300 350 400 pv in1 = 12v i(v batt ) (a) 8603 g09 pv in1 = 24v pv in1 = 36v burst mode operation load current (a) 0.001 0.01 0.1 0.001 1 3 0 10 20 30 40 50 60 70 0.01 80 90 100 efficiency (%) out2 sw 8603 g02 pv in2 = 12v pv in2 = 24v pv in2 = 36v burst mode operation 0.1 load current (a) 0.001 0.01 0.1 1 2 0 10 20 30 1 40 50 60 70 80 90 100 efficiency (%) out3 sw 8603 g03 2 pv in3 = 2.6v pv in3 = 3.3v pv in3 = 5.5v burst mode operation load current (a) 0.001 0.01 0.1 1 2 0 0 10 20 30 40 50 60 70 80 90 10 100 efficiency (%) out1 sw 8603 g04 pv in1 = 12v pv in1 = 24v pv in1 = 36v burst mode operation load current (a) 0.001
7 for more information www.linear.com/lt8603 typical performance characteristics t a = 25c, v in = pv in1 = pv in2 = 12v, en/uvlo = 3v and pv in3 = 3.3v unless otherwise noted. channel 1 peak current limit vs duty cycle channel 2 peak current limit vs duty cycle channel 3 peak current limit vs duty cycle channels 1, 2 minimum on-time vs temperature channels 1, 2 minimum off-time vs temperature channel 3 minimum off-time vs i sw channels 1, 2 minimum on-time vs i sw channels 1, 2 minimum off-time vs i sw channel 3 minimum on-time vs i sw lt8603 8603f 70 144 162 180 minimum on-time (ns) minimum on-time vs i sw 8603 g15 i sw (a) 0.2 0.4 0.6 80 0.8 1 1.2 1.4 1.6 1.8 40 46 52 58 90 64 70 76 82 88 94 100 minimum off-time (ns) minimum off-time vs i sw 8603 g18 100 duty cycle (%) 0 10 20 30 40 50 60 70 80 1.5 90 100 1.5 2.0 2.5 3.0 3.5 4.0 top fet current limit (a) duty cycle 1.8 8601 g12 i sw = 1a ch 1 ch 2 temperature (c) ?50 ?25 0 25 50 2.1 75 100 125 150 40 50 60 70 80 90 2.4 min on-time (ns) minimum on time vs temperature 8603 g16 i sw = 1a ch 1 ch 2 temperature (c) ?50 ?25 0 2.7 25 50 75 100 125 150 50 60 70 80 3.0 90 100 min off-time (ns) minimum off time vs temperature 8603 g17 duty cycle (%) top fet current limit (a) 8603 g10 duty cycle (%) 0 10 20 30 40 50 60 0 70 80 90 100 2.5 3.0 3.5 4.0 4.5 5.0 10 top fet current limit (a) peak current limit vs. duty cycle 8603 g11 ch 1 ch 2 switch current (a) 0 0.5 1 1.5 20 2 2.5 50 60 70 80 90 100 minimum on-time (ns) minimum on time vs i sw 30 8603 g13 switch current (a) 0 0.5 1 1.5 2 2.5 50 60 40 70 80 90 100 minimum off-time (ns) minimum off-time vs i sw 8603 g14 ch 1 ch 2 pv in3 = 2.6v 50 pv in3 = 3.3v pv in3 = 5.5v i sw (a) 0.2 0.4 0.6 0.8 1 1.2 1.4 60 1.6 1.8 0 18 36 54 72 90 108 126
8 for more information www.linear.com/lt8603 t a = 25c, v in = pv in1 = pv in2 = 12v, en/uvlo = 3v and pv in3 = 3.3v unless otherwise noted. por delay time vs temperature feedback voltage vs temperature switching frequency vs r t switching frequency vs temperature por delay vs c por typical performance characteristics channel 4 i lim threshold vs common mode channel 4 i lim threshold vs temperature lt8603 8603f 125 ?8 ?6 ?4 ?2 0 2 4 6 8 10 150 delay time change (%) 8603 g23 v isp , v isn (v) 0 5 10 15 20 25 30 0.990 35 40 45 45 47 49 51 53 55 57 0.995 59 61 63 65 v isp ? v isn (mv) vs common mode 8603 g24 v batt +2v +42v 1.000 temperature (c) ?50 ?25 0 25 50 75 100 125 150 1.005 40.0 42.0 44.0 46.0 48.0 50.0 52.0 54.0 56.0 58.0 1.010 60.0 8603 g25 v isp ? v isn (mv) 0.790 0.795 0.800 temperature (c) 0.805 0.810 ch 1 and ch 2 v fb (v) ch 3 and ch 4 v fb (v) 8603 g19 ch 1 and ch2 ch 3 and ch4 r t (k) 25 50 ?50 75 100 125 150 175 200 225 250 275 0.25 ?25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 frequency (mhz) t 0 8603 g20 r t = 30k r t = 60k r t = 250k temperature (c) ?50 ?25 0 25 50 25 75 100 125 150 ?10 ?8 ?6 ?4 ?2 0 50 2 4 6 8 10 frequency change (%) 8603 g21 c por (pf) 100 1000 75 10000 1 10 100 600 por delay (ms) por 8603 g22 delay time change temperature (c) 100 ?50 ?25 0 25 50 75 100 125 150 ?10
9 for more information www.linear.com/lt8603 channels 3 r ds(on) vs temperature t a = 25c, v in = pv in1 = pv in2 = 12v, en/uvlo = 3v and pv in3 = 3.3v unless otherwise noted. typical performance characteristics channel 1 r ds(on) vs temperature channel 4 minimum on-time vs v isp C v isn channel 4 minimum off-time vs v isp C v isn channel 4 isp, isn input current vs v isp , v isn channel 2 r ds(on) vs temperature channel 1 full frequency v in vs load current channel 2 full frequency v in vs load current channel 3 full frequency v in vs load current lt8603 8603f 75 1.9 2.3 2.6 0 5 10 15 20 25 30 100 35 40 45 v in (v) 8603 g33 r t = 28.7k full frequency region (2mhz) v out = 3.3v v out = 5v 125 i out (a) 0 0.2 0.4 0.6 0.8 1 1.2 150 1.4 1.6 1.8 2 2.0 2.5 3.0 3.5 4.0 4.5 100 5.0 5.5 6.0 v in (v) 8603 g34 r t = 28.7k full frequency region (2mhz) v out = 1.8v v out = 1.2v 200 ch4 f sw = 2mhz 135c 25c ?45c v isp ? v isn (mv) 0 10 20 30 40 300 50 100 120 140 160 180 200 min on?time (ns) isp ? isn 8603 g26 400 for v isp > 2v, 34a typical active < 200na in sleep v isp , v isn (v) ?50 ?40 ?30 ?20 ?10 0 500 10 20 30 40 50 ?8 ?7 ?6 ?5 ?4 r ds(on) (m) ?3 ?3 ?2 ?1 0 1 isp, isn input current(ma) isp , isn 8603 g28 150c bottom fet dson 100c 25c ?45c ch4 switching frequency (mhz) 0 0.5 1 1.5 2 2.5 8603 g29 100 140 180 220 260 300 minimum off-time (ns) 8603 g27 temperature (c) ?50 ?25 0 25 50 75 100 top fet 125 150 0 100 200 300 400 r ds(on) (m) 8603 g30 i sw2 = 1a temperature (c) bottom fet top fet temperature (c) ?50 ?25 0 25 50 75 100 ?50 125 150 0 50 100 150 200 250 300 r ?25 ds(on) (m) 8603 g31 i sw = 1a bottom fet top fet r t = 28.7k full frequency region (2mhz) v out = 3.3v v out = 5v i out (a) 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 25 5 10 15 20 25 30 35 40 45 v in (v) 50 8603 g32 i out (a) 0 0.3 0.7 1 1.3 1.6
10 for more information www.linear.com/lt8603 t a = 25c , v in = pv in1 = pv in2 = 12v , en/uvlo = 3v and pv in3 = 3.3v, unless otherwise noted. typical performance characteristics trkss pull-up current vs voltage rst pull-up current vs voltage channel 2 start-up and dropout, r l = 2 channel 1 start-up and dropout, r l = 20 shutdown i q from the battery overvoltage/temperature en/uvlo current vs voltage lt8603 8603f 3.5 ?3 ?2 ?1 0 1 trkss current (a) 8603 g37 rst voltage (v) 0 trkss voltage (v) 0.5 1 1.5 2 2.5 3 3.5 ?30 ?20 ?10 0 0 10 rst current (a) 8603 g38 100ms/div 2v/div 8603 g39 v out1 v in 100ms/div 0.5 2v/div 8602 g40 v out2 v in v en/uvlo (v) 0 5 10 15 20 1 25 30 35 40 45 0.0 0.5 1.0 1.5 2.0 1.5 2.5 3.0 i en/uvlo (a) 8603 g36 150c 125c 25c ?50c v batt (v) 0 2 5 10 15 20 25 30 35 40 45 0 2.5 1 2 3 4 5 6 7 8 i(v batt ) (ua) q 3 8603 g35
11 for more information www.linear.com/lt8603 radiated emi performance, cispr 25 radiated emission tests with class 5 peak limits t a = 25c typical performance characteristics amplitude (dbv/m) 40 45 50 55 60 35 30 25 20 15 10 ?15 0 ?5 ?10 5 frequency (mhz) 30 930 130 230 330 530 430 630 730 830 1030 cispr 25 class 5 peak limit data lt8603 8603f 8603 emi 01a vertical polarization peak detector dc2114a demo board (with emi filter installed) v batt = 14v, v out1 = 5v, v out2 = 3.3v, v out3 = 1.8v, i out1,2,3 = 1a f sw = 2mhz, fsela = intv cc , fselb = ground
12 for more information www.linear.com/lt8603 pin functions pg1, pg2, pg3 (pins 1, 10, 40): power good indicators for channels 1, 2 and 3, respectively. these pins are open- drain outputs that pull down until the associated fb pin is within 8% of the target regulation voltage. gnd (pins 2, 8, 13, 35, 38, exposed pad 41): ground. all ground pins and the exposed pad must be soldered to pcb ground. see the applications information section for pcb layout recommendations. sw1 (pin 3): high voltage converter 1 switch node. this is the output of the internal power switches for channel 1. bst1, bst2 (pins 4, 5): boost voltage for high voltage converters. these pins provide the drive voltage required by the internal power mosfets. a capacitor should be connected from bst to the associated sw pin. sw2 (pins 6, 7): high voltage converter 2 switch node. this is the output of the internal power switches for channel 2. these pins should be soldered to the same pcb trace for even current distribution. bias (pin 9): alternate power source for intv cc and intv cc4 regulators. if bias > 3.1v for intv cc or > 4.6v for intv cc4 the internal regulators will draw their power from bias. this will reduce the on-chip power dissipation during full frequency operation and reduce the effective no-load sleep current at the input. pg4 (pin 11): power good indicator channel 4. this pin is an open-drain output that pulls low until the channel 4 feedback voltage is greater than 92% of its reference voltage. fsel4a, fsel4b (pins 12, 17): boost converter frequency select and run control. these pins are logic inputs. when both pins are low, the boost controller is shut down. the boost controller switching frequency is controlled using these pins according to table 2 in the applications information section. g at e4 (pin 15): external mosfet gate drive output. this pin switches from gnd to v intvcc4 to turn on the low side power mosfet in the boost converter. see the applications information section for information on mosfet selection. intv cc4 (pin 16): internal boost regulator output. do not load the intv cc4 pin with external circuitry. intv cc4 is 4.6v when bias < 4.6v, 5v when bias > 5v, and equal to bias when bias is between 4.6v and 5v. decouple to ground with a low esr 4.7f capacitor. isp4, isn4 (pins 19, 18): boost controller current sense inputs. connect a current sense resistor of appropriate value between these pins with isp4 connected to the input supply and is n4 to the application inductor. see the applications information section for sense resistor selection details. trkss1, trkss2 (pins 21, 20): track/soft-start inputs for the high voltage converters. when this pin is below 1v, the converter regulates the fb pin to the trkss volt - age instead of the internal reference. the trkss pin has a 2.4a pull-up current. connect a capacitor between either of these pins to ground to program a soft-start time for the associated channel. en/uvlo (pin 22): enable/undervoltage lockout input. the lt8603 is in low power shutdown when this pin is below 0.4v . between 0.4v and 1.1v, the part will turn on the internal reference. a precision threshold at 1.2v?(ris - ing) enables the switching regulators. the precision threshold allows the en/uvlo pin to be used as an input undervoltage lockout by connecting to resistor divider between v in and gnd. when the en/uvlo voltage is between 0.4v and 1.2v, the lt8603 input current will depend on the mode selected, the v in voltage and en/ uvlo voltage. v in (pin 23): power supply to internal functions. this pin provides power to the lt8603 internal circuitry. this pin must reach 4v for the boost converter to complete its internal soft-start delay of 1ms. fb4 (pin 24): feedback input pin for the boost converter. the converter regulates fb4 to 0.8v. fb1, fb2 (pins 26, 25): feedback input pins for the high voltage converters. the converters regulate the lt8603 8603f
13 for more information www.linear.com/lt8603 corresponding feedback pin to the lesser of 1v or the voltage on the associated trkss pin. fb3 (pin 27): feedback input pin for the low voltage converter. the converter regulates fb3 to 0.8v. intv cc (pin 28): internal regulator bypass. do not load the intv cc pin with external circuitry. intv cc is 3.1v when bias < 3.1v, 3.4v when bias > 3.4v, and equal to bias when bias is between 3.1v and 3.4v. decouple to ground with a low esr 4.7f capacitor. rt (pin 29) : frequency programming resistor. connect a resistor between this pin and ground to set the internal oscillator frequency. this pin should not be left open. run3 (pin 30): enable input for low voltage channel 3. channel 3 is enabled when the voltage on this pin exceeds 1.2v. the run3 pin has a precise threshold so it can be used to create a uvlo function or be sequenced from another channel. there is an internal soft-start timer which ramps the output up in approximately 1ms. cpor (pin 31): power-on reset timing capacitor. a?capacitor from this pin to ground sets the period of the power-on reset oscillator timer. see the applications information section for details. rst (pin 32): active low reset output. this pin is the output of the power-on reset function. this pin is an open- drain output with a weak pull-up to approximately 2v . this pin is held low until the power on reset timer times out. sync (pin 33) : clock synchronization and mode select input. this pin allows the lt8603 to synchronize its switching frequency to an external clock. when an external clock is applied, the lt8603 will operate in pulse-skipping mode. if clock synchronization is not used, connect this pin to ground to enable low ripple burst mode operation or connect high to enable pulse-skipping operation. pv i n3 (pin 34): input supply voltage to low voltage channel 3. this pin will normally be connected to the output of one of the high voltage converters but can be supplied from any voltage in the specified range. it should be bypassed locally with a low esr ceramic capaci- tor to ground with a low inductance connection to the exposed?pad. sw3 (pin 36): low voltage converter switch node. this is the output of the internal power switches for channel 3. pv in1 , pv in2 (pins 37, 14): input supply to high voltage channels 1 and 2, respectively. these pins can be pow - ered from the boost converter output or any voltage in the specified range. each pin should be bypassed locally with ?a low esr ceramic capacitor to ground with a low inductance connection to the exposed pad. poren (pin 39): power-on reset enable. this is a logic input that starts the ramp on the por timing capacitor. this input has a weak pull-up to allow direct connection to open-drain outputs. pin functions lt8603 8603f
14 for more information www.linear.com/lt8603 block diagram 8603 bd 2.4a 1v fb2 gate4 i lim2 + ? error amplifier bst1 bst2 rst loop compensation logic 4 + 1.08v 0.92v ? + trkss2 pg2 isn4 driver gnd run3 isp4 sw2 pv in2 i lim2 i lim3 i lim1 logic 2 clk4 clk2 clk1 clk1 + ? intv cc gnd driver driver driver current sense comparator current sense comparator reverse current comparator current sense comparator reverse current comparator reverse current comparator slope4 clk4 clk2 clk1 ss4 2.4a ss3 0.8v 1v 0.8v fb4 fb1 sw3 pv in3 trkss1 pg1 gnd sw1 pv in1 gnd fb3 i lim4 i trip i lim1 i lim3 + ? error amplifier error amplifier loop compensation + 0.736v 1.08v 0.92v 0.864v 0.736v pg4 pg3 + ? + + ? + ? + ? + ? + ? cpor poren + ? + loop compensation loop compensation bias v in power-on reset fsel4b fsel4a boost divider and slope gen sync rt oscillator reference standby/bias intv cc4 regulator intv cc regulator en/uvlo logic 3 logic 1 + ? + ? + ? + ? 1v intv cc intv cc4 intv cc4 intv cc4 3.4v 5v 0.8v 1.2v + ? current comparator error amplifier lt8603 8603f
15 for more information www.linear.com/lt8603 operation the lt8603 combines two 42v input step-down convert - ers (channels 1 and 2), one 5.5v input step-down con - verter (channel 3) and a boost controller (channel?4) to provide a flexible system that can be configured to gener - ate up to four regulated outputs. for example, the boost controller may be used to guarantee a supply to the high voltage converters above their minimum dropout voltage even during the cold crank cycle in an automobile. start-up when enabled by setting the en/uvlo voltage above its threshold, the lt8603 intv cc regulator charges its output capacitor to supply the internal chip circuitry. if bias is higher than 3.1v , bias supplies current to the intv cc regulator to reduce v in quiescent current. the boost controller is enabled with a logic high on either one or both of the fsel4a and fsel4b pins. once enabled, the intv cc4 regulator charges its output capaci - tor bringing the intv cc4 supply into regulation. when the voltage at intv cc4 exceeds 4.0v , the boost controller gate driver will begin supplying gate drive pules to the external mosfet. like the intv cc regulator, the intv cc4 regulator can also draw power from the bias pin when bias exceeds 4.6v. high voltage buck regulators (channels 1 and 2) each high voltage channel is a synchronous buck regu - lator that operates from an independent pv in pin. the internal top power mosfet is turned on at the beginning of each oscillator cycle, and turned off when the current flowing through the top mosfet reaches a level deter - mined by the error amplifier. the error amplifier measures the output voltage through an external resistor divider tied to the fb pin to control the peak current in the top switch. the reference of the error amplifier is determined by the lower of the internal 1v reference and the voltage at its trkss pin. while the top mosfet is off, the bottom mosfet is turned on for the remainder of the oscillator cycle or until the inductor current starts to reverse. if overload conditions result in more than 2a for channel 1 or 3.3a for channel?2 flowing through the bottom switch, the next clock cycle will be delayed until switch current returns to a safe level. the trkss pins can be used for controlled start-up or tracking of another supply. low voltage buck regulator (channel 3) the low voltage channel is a synchronous buck regulator that operates from an independent pv in pin. the pv in pin has an undervoltage lockout set at 2.35v. the top power mosfet is turned on at the beginning of each oscillator cycle, and turned off when the current flowing through the top mosfet reaches a level determined by the error amplifier. the error amplifier measures the output voltage through an external resistor divider tied to the fb3 pin to control the peak current in the top switch. the reference of the error amplifier is an internal 800mv reference. while the top mosfet is off, the bottom mosfet is turned on for the remainder of the oscillator cycle or until the induc - tor current starts to reverse. if overload conditions result in more than 2.4a flowing through the bottom switch, the next clock cycle will be delayed until switch current returns to a safe level. the low voltage channel has a run3 pin to allow power sequencing, plus an internal soft-start circuit that ramps the output voltage up in 1ms. boost controller (channel 4) the boost controller includes an error amplifier, loop compensation, current comparator, switch control logic, and a gate driver. the controller is enabled and its clock frequency selected by control of the fsel4a and fsel4b pins as described in the applications information section. the required external n-channel mosfet is turned on by the internal clock and turned off when the inductor current sensed by the current comparator exceeds its threshold. the error amplifier adjusts the current com - parator threshold by comparing the fb4 voltage to an internal 0.8v reference voltage. the output voltage is set by a resistor divider from the output to the fb4 pin. the internal intv cc4 regulator provides the gate drive for the external mosfet. lt8603 8603f
16 for more information www.linear.com/lt8603 operation multiphase switching the oscillator generates two clock signals 180 out of phase with each other. channels 1 and 3 operate from clk1 , while channels 2 and 4 operate from clk2 . the clock for channel 4 may be selected as either a 1, 2?or? 5 version of clk2 using the fsel4a and fsel4b pins. regardless of the divide ratio chosen, the channel?4 clock edges remain aligned to the clk2 edges. since a buck regulator only draws input current during the top switch on cycle, multiphase operation reduces peak input current and doubles the input current frequency. these effects reduce input current ripple and reduce the input capacitance required. undervoltage lockout the en/uvlo pin is used to put the lt8603 in shutdown, reducing the input current to less than 1a . the accurate 1.2v threshold of the en/uvlo pin provides a program - mable v in undervoltage lockout through an external resis - tor divider tied to the en/uvlo pin. a 50mv hysteresis voltage on the en/uvlo pin prevents switching noise from inadvertently shutting down the lt8603. power good comparators channels 1, 2 and 3 have power good comparators that trip when the feedback pin is more than 8% above or below its reference voltage. channel 4 has a power good comparator that indicates when the output voltage is more than 8% below its reference. the pg output pins are open- drain and pulled low when the corresponding output is out of regulation. the pg outputs are not valid until intv cc rises to 2.7v. power-on reset timer the lt8603 includes a power-on reset timer. the power-on reset timeout period is adjustable using an external capacitor on the cpor pin as described in the applications information section. the timer is initiated when the poren pin is higher than 1.2v. the output of the por timer, the rst pin, is an open-drain output with a weak internal pull-up of 100k to approximately 2v. rst is held low until the expiration of the por timer. the rst pin is only valid when the lt8603 is enabled and intv cc is above 2.7v. lt8603 8603f
17 for more information www.linear.com/lt8603 applications information system architecture the lt8603 combines three buck converters with a boost controller to provide a flexible system supply that can be configured to generate up to four regulated outputs. the 4 channels are independently powered and can be connected in a variety of ways. for example, the output of the boost may be used to supply the input voltage to the buck converters resulting in three tightly regulated outputs even when the boost input voltage falls below the? regulated buck outputs such as occurs during an automotive cold crank scenario. alternatively, if the boost controller is driven from a buck output or is configured as a sepic converter, the lt8603 provides up to four tightly regulated outputs. v in voltage range the minimum voltage at v in for the lt8603 internal cir - cuitry and the buck converters to start is 3.1v , however, at least 4v is required for the boost controller and the intv cc4 regulator to start. the boost controller can be configured to supply v in and the pv in pins once it has started; after start-up the input voltage to the boost con - troller can go lower than 3v. enable and under voltage lockout the en/uvlo pin can be used to to program a minimum system start voltage or an undervoltage lockout (uvlo) voltage. it has an internal threshold of 1.2v with 50mv hysteresis. the uvlo divider circuit is shown in figure 1. the uvlo threshold is given by: v uvlo ( ) = r uv1 + r uv 2 r uv 2 ? 1.2v switching frequency all 4 channels share a single oscillator. the buck chan - nels switch at the oscillator frequency. the boost chan - nel can switch at f osc , f osc /2 or f osc /5. the switching frequency range of all 4 channels should be determined before selecting the oscillator frequency. a low frequency usually provides better efficiency and a wider operating range due to lower switching losses and less sensitivity to timing constraints such as minimum on- and off-times. a high switching frequency uses smaller components and moves the switching noise away from sensitive frequency bands, such as the am radio band, but does so at the cost of lower efficiency. a high switching frequency also decreases the duty cycle range because of finite mini - mum on- and off-times which are independent of the switching?frequency. the oscillator frequency can be programmed from 250khz to 2.2mhz by tying a resistor from the rt pin to ground. table 1 shows the necessary value of r t for some com - mon switching frequencies. table 1. oscillator frequency (f osc ) vs r t value oscillator frequency (mhz) r t (k) 0.25 244 0.35 173 0.5 120 0.75 79.2 1.0 58.9 1.25 46.8 1.5 38.7 1.75 33.0 2.0 28.7 2.2 26.0 the following equation approximates the values shown in table 1: r t = 59.8 (f osc C 0.007) C 1.3 the rt pin is sensitive to noise so the resistor should?be placed close to the lt8603 and away from noise sources. figure 1. uvlo divider 8603 f01 en/uvlo lt8603 v in v in or v batt r uv1 r uv2 lt8603 8603f
18 for more information www.linear.com/lt8603 pin is connected to a switching regulator channel it will improve efficiency, reduce on-chip dissipation and lower the sleep current. the intv cc may be used to configure other inputs and supply pull-ups related to the lt8603. it is not recommended to draw more than 1ma or connect intv cc to any components not related to the lt8603 to avoid unexpected interactions. boost controller functional description channel 4 is a set of functional elements that are con - nected to external components to form a boost converter. the block diagram in figure 2 shows these elements and how they are connected internally. the error amplifier compares a fractional part of the out - put voltage to an 800mv reference. the output, i lim4 , goes to the current comparator to set the peak current. the current comparator senses the inductor current using a small sense resistor across the isp4 and isn4 pins. the trip level is set by the error amplifier output, i lim4 , and the slope compensation signal, slope4. the maximum the internal oscillator of the lt8603 can be synchronized to an external clock of 250khz up to 2.2mhz applied to the sync pin. the r t value should be chosen such that the frequency set by r t is close to the anticipated external clock frequency. mode selection and synchronization to select low ripple burst mode operation, the sync pin should be connected to a voltage below 0.3v such as ground. to select pulse-skipping operation, connect the sync pin to an available voltage above 1.2v such as?intv cc . to synchronize the lt8603 to an external frequency, drive the sync pin with a pulse train with a high voltage above 1.2v and a low voltage below 0.3v. the minimum pulse width is 120ns for a high pulse and 90ns for a low pulse. the lt8603 will operate in pulse-skipping mode while synchronized to an external clock. the lt8603 may be synchronized over a 250khz to 2.2mhz range. the r t resistor should be chosen to set the lt8603 switching frequency close to the synchronization input. for some applications it is desirable for the lt8603 to operate in pulse-skipping mode, offering two major differ - ences from burst mode operation. first, in pulse-skipping mode the clock stays awake at all times and all switching cycles are aligned to the clock. second, full frequency switching is reached at a lower output load in pulse-skip - ping?than burst mode operation. these two differences come at the expense of increased quiescent current for pulse-skipping. to enable pulse-skipping mode, the sync pin is tied high either to a logic output or to the intv cc pin. do not leave the sync pin floating. intv cc regulator the intv cc supplies the common circuitry such as the oscillator and reference but its main current demand comes from the gate drivers for the high voltage buck converters. the current draw will depend on the operat - ing frequency, the higher the switching frequency, the greater the current drawn from intv cc . the regulator is supplied by v in at start-up, but it will draw its supply current from bias if bias is at least 3.1v . if the bias applications information figure 2. boost controller block diagram 8603 f02 gate4 logic 4 ? + isn4 driver isp4 clk4 ss4 0.8v fb4 i lim4 i trip + ? loop compensation + 0.736v pg4 bias v in fsel4b fsel4a boost divider and slope gen intv cc4 regulator + ? intv cc4 5v current comparator error amplifier clk2 slope4 lt8603 8603f
19 for more information www.linear.com/lt8603 trip level is 50mv. isp4 and isn4 have an operational common range of 2v to 42v and an absolute maximum rating of 42v . this allows reverse battery protection with a single diode in series with external mosfet drain. the logic block turns on the external mosfet on a clk4 signal, and then turns it off on an i trip from the current comparator, or when maximum duty cycle is reached. the lt8603 has a frequency divider that allows the con - troller switching frequency to be less than the oscilla - tor frequency. the boost controller is specified for a f sw between 250khz and 2.2mhz; do not set the divider to operate the boost controller below 250khz. the fsel4a and fse l4 b pins control the oscillator frequency as shown in table 2. table 2. boost frequency selection boost freq f sw4 fsel4a fsel4b 0 (boost shutdown) low low f osc /5 high low f osc /2 low high f osc high high the boost controller is enabled by the fse l4 a and fse l4 b pins. when both pins are low, the boost controller is shut down. when either or both pins are set high, a boost controller start-up sequence is initiated. during start-up, the intv cc4 regulator is turned on charging the external intv cc4 capacitor. once intv cc4 reaches 4v, the control - ler logic is turned on and switching begins. a 1ms soft- start ramp is applied to the error amplifier to minimize inrush current. the intv cc4 regulator is a low dropout, linear regulator that provides power to the gat e4 drive circuit. it is dedi - cated to the boost controller and is shut down when the boost controller is shut down. it can draw power from either v in or bias, depending on the bias voltage. when bias is less that 4.6v, the regulator will draw power from v in and regulate to 4.6v. when bias is greater than 4.6v but less than 5v , the regulator sets intv cc4 equal to bias and draws power from bias. when bias is greater than 5v, the regulator generates 5v and draws power from bias. do not use the intv cc4 output for external circuitry. a comparator senses when the output voltage is above 92% of the programmed value and generates a power good signal at the pg4 pin. setting the output voltage the boost controller s output voltage is set by connecting the fb4 pin to a resistor divider from the output as shown in figure 3. applications information figure 3. feedback resistor divider the value of r2 is best selected first as this establishes how much current is in the string based on i = v fb4 /r2 where v fb4 = 0.8v . the current should be chosen such that it is not influenced by anticipated leakage or noise. r1 can then be calculated from: r1 = r2 ? ((v out4 /v fb4 ) C 1) boost configuration the lt8603 boost controller configured as a standard boost regulator is shown in figure 4. the boost control - ler output voltage is set by connecting fb4 to an external divider . for the following example, r2 and r3 are chosen such that out4 = 8v . if the battery voltage (v batt ) is above 8v plus a diode forward voltage, the boost control - ler will be inactive consuming minimal quiescent current. if the battery voltage drops below 8v plus a diode forward voltage, such as during an automotive cold crank cycle, the boost controller will become active to maintain 8v at out4. with out4 connected to v in , the input supply must reach 4v plus the diode forward voltage to start. 8603 f03 fb4 v out4 r1 r2 lt8603 lt8603 8603f
20 for more information www.linear.com/lt8603 once started however, the lt8603 will maintain the output voltage at out4 with v batt as low as 2v. the isp4 and isn4 pins sense the inductor current for the current mode control loop across current sense resistor r1 . the isp4 and isn4 pins will accurately sense the inductor current down to 2v and will tolerate negative voltages as large as C42v without damage. by adding diode sd2 in series with the main switch tran - sistor m1 , the entire regulator will be tolerant of negative input supply voltages. one of the limitations of the boost configuration is that it cannot provide short-circuit protection for the boost output as the diode always provides a dc current path from input to output. if short-circuit overload protection is required the sepic configuration should be considered. see the sepic configuration section for more information on the sepic converter. boost: duty cycle and max switching frequency in continuous conduction mode (ccm), the operating duty cycle as a function of input and output voltage is given by: d = v out + v d C v batt v out + v d ? ? ? ? ? ? ? ? ? ? where v d is the forward voltage drop of the diode. applications information thus the maximum duty cycle (d max ) in terms of the minimum v batt is: d max = v out + v d C v batt min ( ) v out + v d for a given input and output voltage, the switching fre - quency is limited by the expected maximum duty cycle, d max , and minimum switch off time, t off(min) . the f sw(max) at d max is given by: f sw(max) = d max t off(min) boost: inductor and sense resistor selection the boost regulator inductor and sense resistor (r sense ) should be sized according to the maximum input cur - rent. the maximum input current will occur at the mini - mum input voltage (maximum duty cycle) and maximum output?load. the maximum average inductor current, which is equal to the average input current, can be calculated from: i l(max ) = i out(max ) 1 C d max figure 4. channel 4 in boost configuration 8603 f04 l1 sd1 v batt lt8603 fb4 gate4 en/uvlo c1 intv cc4 isn4 isp4 fsel4a fsel4b gnd r1 c3 rt v in sd2* m1 c2 *sd2 is for reverse input protection. short if not needed. r2 r3 intv cc4 intv cc v out 4 = 0.8 ? (r2 + < v out 4 + v f(sd1) = v batt ?v f(sd1) = whenv batt v out 4 + v f(sd1) lt8603 8603f
21 for more information www.linear.com/lt8603 applications information from this the ripple current can be specified using: ?i l = ?i l(max ) = ?i out(max ) ? 1 1 C d max where in the above equation represents the percent - age peak-to-peak ripple current in the inductor relative to i l(max) . choosing the inductor ripple current, ?i l , has a direct impact on the choice of the inductor value and the converter s maximum output current capability. choosing smaller values of ?i l increases the converter s output cur - rent capability but requires larger inductors. choosing larger values of ?i l provides faster transient response and allows the use of smaller inductors but results in higher input current ripple, greater core losses, and lower output current capability. in addition, larger values of ?i l at high duty cycle may result in sub-harmonic oscillation. the typical range for is 20% to 40% though careful evaluation of system stability should be made to ensure adequate design margin. the peak inductor current will be the average inductor current plus half the ripple current. the lt8603 current sense comparator has a built-in cur - rent limit threshold of 50mv across isp4 and isn4 so the peak voltage across the sense resistor should be kept to no more than 80% of this or 40mv . therefore, the value of r sense should be: r sense = 0.04 i l(peak ) i l(peak) can be calculated from: i l(peak ) = 1 + 2 ? ? ? ? ? ? ? ? ? i out(max ) 1 C d max the inductor value to achieve the required ripple is given by following equation: l = v batt min ( ) ?i l ? f sw ? d max the inductor should have a saturation current exceeding the current limit value of: i lim = 0.05 r sense finally, the esr and magnetic loss of the inductor con - tribute to overall system power loss. for best efficiency, an inductor with low esr and a core rated for the desired operating frequency should be chosen. the sense resis - tor should be chosen to have adequate power handling capability . the maximum power dissipation is given by: p rsense = 0.05 2 r sense for example, a 4m? could dissipate up to 0.625w. boost: mosfet selection for the boost configuration, the selected external mosfet should have a bv dss rating exceeding, with margin, the larger of either the maximum input voltage or the boost output voltage plus a diode forward voltage. the maxi - mum input voltage should include careful consideration of possible transient conditions. in addition, the chosen mosfet should be compatible with the lt8603 s nomi - nal gate drive of 4.6v and have a low value of r ds(on) for best efficiency. the current rating for the mosfet must be greater than the peak inductor current. finally, the maximum gate drive current required by the external mosfet should not exceed the 40ma capability of the lt8603. the current drawn by the gate driver is given by: i drive = q g ? f sw where q g is the mosfet gate charge and f sw is pro - grammed switching frequency. for example, if q g is 20nc and f sw is 1mhz , the drive requirement is 20ma. boost: diode selection in the boost converter, the rectifier diode, sd1 , only con - ducts when the switch is off. the average diode current is equal to the output current. the peak current is equal to the peak inductor current and is given by : i d peak ( ) = 1 + 2 ? ? ? ? ? ? ? ? ? i out max ( ) 1 C d max lt8603 8603f
22 for more information www.linear.com/lt8603 applications information the power dissipated by the diode is given by: p d = i out max ( ) ? v d therefore, a rectifier diode should be chosen with a low forward voltage drop at peak current for best efficiency and a reverse breakdown voltage greater than v out4(max) . if the reverse protection diode ( sd2 ) is needed, the reverse breakdown voltage must be greater than the desired reverse polarity protection. boost: output capacitor the output capacitor has two essential functions. first, the output capacitor filters the lt8603 s discontinuous output current to produce the dc output current. in this role, the capacitor determines the output ripple, thus low imped - ance at the switching frequency is important. second, the output capacitor stores energy in order to satisfy transient load conditions and stabilize the lt8603s control loop. typically, the low equivalent series resistance of x5r and x7r ceramic capacitors provide low output ripple and good transient response. for some applications, transient performance can be improved with higher output capacitance and/or the addition of a feedforward capacitor placed between the boost output voltage and the boost feedback pin. note that larger output capacitance may be required when lower switching frequencies are used or when there is signifi- cant inductance to the load due to long wire or cables. increasing the output capacitance will also decrease the output ripple. when choosing a capacitor , special attention should be given to the capacitor s data sheet to understand the effective capacitance under the relevant operating condi - tions of voltage bias and temperature. for good starting values, refer to the typical applications section. for all applications, careful evaluation of system stability should be made to ensure adequate design margin. boost: input capacitor the input capacitor is in series with the inductor so the input current waveform is continuous and the d i /d t is limited. an input capacitor should be chosen to handle the rms input capacitor ripple current as given by: i rms cin ( ) = 0.6 ? ? i outmax figure 5. switching waveforms for a boost converter v batt l d sw 5a. circuit diagram 5b. inductor and input currents c out v out r l i in i l 5c. switch current i sw t on 5d. diode and output currents 5e. output voltage ripple waveform i o i d t off 8603 f05 v out (ac) v esr ringing due to total inductance (board + cap) v cout lt8603 8603f
23 for more information www.linear.com/lt8603 applications information ensure that capacitors present at the input are rated to withstand any voltage transients that may be applied. the value of input capacitance is a function of the source impedance. in general, the higher the source impedance, the higher the required input capacitance. the typical applications section provides reasonable starting values for input capacitance but careful evaluation of each appli - cation must be made to ensure adequate design margin. sepic configuration figure 6 shows the boost controller configured as a sin - gle-ended primary inductance converter or sepic. the sepic configuration offers two primary advantages over the standard boost configuration. first, it operates like a buck/boost which means it will regulate to an accurate output voltage for any input voltage. second, it offers short-circuit protection and 0v output in shutdown since there is no dc path from the input to the output. the dis - advantage is a more complex circuit requiring additional components as compared to a standard boost configura - tion. since there is no dc path to the output, the lt8603 v in cannot be connected directly to the sepic output. as a result, diode sd3 is used to ensure start-up, and sd4 is used to ensure operation to low v batt once started. if v batt drops below 4v after the sepic is in regulation, sd4 maintains v in at the sepic output voltage. just as with the standard boost configuration, optional diode sd2 provides reverse battery protection. figure 7 shows a simplified topology and the current flow for each of the switch positions once steady state is reached. both inductors increase current during the switch on cycle (figure 7b ). the dc currents of l1 and l2 are not necessarily equal: i l1(dc) must be equal to i vbatt(dc) since there is no other dc path for the current flow from v batt . by the same argument, i l2(dc) must be equal to i out(dc) . figure 8 shows the current waveforms of the sepic converter. although uncoupled inductors can be used in the sepic converter, coupled inductors provide several advantages and are preferred for most applications. uncoupled induc - tors require double the inductance of the coupled induc- tors and two inductors at twice the inductance usually cost more than one coupled inductor. also, uncoupled inductors form a tank with the coupling capacitor which can ring at very low frequencies. uncoupled inductors can be an advantage, however, in high power or high duty cycle converters since the current is split between two?cores. figure 6. channel 4 in sepic configuration 8603 f06 l1 sd1 v batt lt8603 fb4 gate4 en/uvlo c1 c4 intv cc4 isn4 isp4bias fsel4a fsel4b gnd r1 c3 rt v in sd2* sd3 m1 c2 *sd2 is for reverse input protection. short if not needed. r2 r3 intv cc4 intv cc 5v v out 4 = 0.8 ? (r2 + r3) r3 sd4 ? c5 ? l2 lt8603 8603f
24 for more information www.linear.com/lt8603 applications information the lower of these frequencies is the maximum switching frequency for the sepic converter. sepic: inductor and r sense selection choosing the inductor ripple current, ?i l , has a direct impact on the choice of the inductor value and the con - verter s maximum output current capability. choosing smaller values of ?i l increases the converter s output current capability but requires larger inductors. choosing larger values of ?i l provides faster transient response and allows the use of smaller inductors but results in higher input current ripple, greater core losses, and lower output current capability. in addition, larger values of ?i l at high duty cycle may result in sub-harmonic oscillation. given an operating input voltage range and operating fre - quency, the inductor value is given by: l = v batt(min) ? d max ? i l ? f sw where, ? i l = ? i out(max) ? d max 1C d max in the above equation represents the percentage peak- to-peak ripple current in the inductor relative to the maxi - mum average inductor current. the typical range of is 20% to 40% though careful evaluation of system stability should be made to ensure adequate design margin. for coupled inductors, l1 = l2 and the effective induc - tance is doubled due to the mutual inductance. the value of each equal winding is given by : l1 = l2 = v batt(min) ? d max 2 ? ? i l ? f sw the maximum input current of the sepic converter is cal - culated at the minimum input voltage and full load current. the peak inductor current can be significantly higher than the output current. the following equations assume ccm operation and calculate the maximum peak inductor cur - rent at minimum v batt : figures 7. sepic topology and current flow + + + ? ? ? ? sw l2 c out r l v out c1 d1 l1 l2 l1 l2 l1 7a. sepic topology + + + ? r l v out d1 7c. current flow during switch off-time + + + ? r l v out v in v in 7b. current flow during switch on-time 8603 f07 v batt v batt v batt sepic: duty cycle and frequency with the sepic configuration operating in continuous conduction mode (ccm), the duty cycle is given by: d = v out + v d v batt + v out + v d ? ? ? ? ? ? ? ? ? ? the maximum switching frequency of the sepic con - verter is limited by both maximum and minimum duty cycles. the maximum duty cycle is set by v batt(min) . the maximum switching frequency, f sw(max) at v batt(min) is given by: f sw(max)@v batt(min) = 1 C v out + v d v batt(min) + v out + v d ? ? ? ? ? ? ? ? ? ? t off(min) the minimum duty cycle is set by v batt(max) . the maxi- mum switching frequency at v batt(max) is given by: f sw(max)@v batt(max) = v out + v d v batt(max) + v out + v d ? ? ? ? ? ? ? ? ? ? t on(min) lt8603 8603f
25 for more information www.linear.com/lt8603 applications information for a coupled inductor: i l(peak ) = 1 + 2 ? ? ? ? ? ? ? ? ?i out(max ) ? 1 + v out + v d v batt(min) ? ? ? ? ? ? ? ? ? ? for uncoupled inductors: i l1(peak ) = 1 + 2 ? ? ? ? ? ? ? ? ?i outmax ? v out + v d v batt(min) i l2(peak ) = 1 + 2 ? ? ? ? ? ? ? ? ?i out(max ) ? v batt(min) + v d v batt(min) r sense can then be calculated by: r sense = 0.04 i l1(peak ) the chosen inductor(s) should be rated for the maximum expected current. sepic: mosfet selection for the sepic configuration, the selected mosfet should have a bvd ss rating exceeding, with margin, the maxi - mum input voltage plus the maximum output voltage plus the maximum diode forward voltage. the maximum input voltage should include careful consideration of possible transient conditions. in addition, the chosen mosfet should be compatible with the lt8603 s nominal gate drive of 4.6v and have a low value of r ds(on) for best efficiency. the current rating for the mosfet must be greater than the peak switch current of: i sw(peak) = 1 + 2 ? ? ? ? ? ? ? ? ? i out(max) ? 1 1C d max finally, the maximum gate drive current required by the external mosfet should not exceed the 40ma capability of the lt8603. the current drawn by the gate driver is given?by: i drive = q g ? f sw figure 8. sepic converter switching waveforms 8a. input inductor current i in i l1 sw on sw off 8b. output inductor current i o i l2 8c. dc coupling capacitor current i o i in i c1 8e. output ripple voltage v out (ac) v esr ringing due to total inductance (board + cap) v cout 8d. diode current i o i d1 8603 f08 sepic: diode selection for the rectifier diode, sd1, the peak reverse voltage that the diode must withstand is: v batt(max ) + = 1 + 2 ? ? ? ? ? ? ? ? ?i out(max ) ? v out + v d v batt(min) + 1 ? ? ? ? ? ? ? ? ? ? lt8603 8603f
26 for more information www.linear.com/lt8603 applications information the power dissipated by the diode is: p d = i out(max ) ? v d if the reverse protection diode, sd2, is needed, the peak reverse voltage must be greater than the maximum reverse polarity input expected. the average forward cur - rent is equal to the input current and the peak forward current is the same as for the rectifier diode above. the start-up diodes, sd3 and sd4, have modest current requirements; the forward current will be less than 50ma under all input conditions. the peak reverse voltage on sd3 is the maximum reverse polarity input expected and the peak reverse voltage on sd4 is the maximum input?voltage. sepic: dc-coupling capacitor the dc-coupling capacitor cc (c5 in figure 6) sees a nearly rectangular current waveform as shown in figure? 8c. during the switch off time, the current through cc is approximately i in , and approximately Ci out during the switch on time. this current ripple creates a triangular ripple voltage on cc: ? v cc(p ? p) = i out(max ) cc ? f sw ? v out v batt + v out + v d the maximum voltage on cc is then: v cc(max ) = v batt(max ) + ? v cc(p ? p) 2 which is typically close to v batt(max) . the ripple current through cc is: i rms(cc) = i out(max ) ? v out + v d v batt(min) the capacitance value should be chosen large enough that ?v cc(p-p) is less than 10% of v batt(min) . if ?v cc(p-p) is small then the voltage rating is close to v batt(max) . sepic: output capacitor the output capacitor has two essential functions. first, the output capacitor filters the lt8603 s discontinuous output current to produce the dc output current. in this role, the capacitor determines the output ripple, thus low imped - ance at the switching frequency is important. second, the output capacitor stores energy in order to satisfy transient load conditions and stabilize the lt8603s control loop. typically, the low equivalent series resistance of x5r and x7r ceramic capacitors provide low output ripple and good transient response. for some applications, transient performance can be improved with higher output capacitance and/or the addition of a feedforward capacitor placed between the output voltage and the feedback pin. note that larger out - put capacitance may be required when lower switching frequencies are used or when there is significant induc - tance to the load due to long wire or cables. increasing the output capacitance will also decrease the output ripple. when choosing a capacitor, special attention should be given to the capacitor s data sheet to understand the effective capacitance under the relevant operating condi - tions of voltage bias and temperature. for good starting values, refer to the typical applications section. for all applications, careful evaluation of system stability should be made to ensure adequate design margin. sepic: input capacitor the input capacitor is in series with the inductor so the input current waveform is continuous and the d i /d t is?limited. an input capacitor should be chosen to handle the rms input capacitor ripple current as given by: i rms cin ( ) = 0.3 ? v batt min ( ) l ? f sw ? d max ensure that capacitors present at the input are rated to withstand any voltage transients that may be applied. lt8603 8603f
27 for more information www.linear.com/lt8603 applications information limitations on the achievable duty cycle range and oper - ating frequency. for buck regulators, the duty cycle is given by: d = v out pv in further, the minimum duty cycle achievable at a given operating frequency is given by: d min = t on(min) ? f sw where f sw is the programmed operating frequency. the maximum duty cycle achievable at a given operating frequency is given by: d max = 1 C (t off(min) ? f sw ) combining these equations, the minimum pv in voltage allowed while regulating at full frequency is: pv inx(min) = v outx 1 C (t off(min) ? f sw ) and the maximum v in voltage allowed while regulating at full frequency is: pv inx(max) = v outx t on(min) ? f sw if the pv in(max) given above is exceeded during regula - tion, the buck regulator will skip switch-on cycles and no longer maintain the programmed operating frequency . buck: inductor selection inductor selection involves inductance, saturation current, series resistance (dcr) and magnetic loss. a good starting point for choosing inductor values is: l = 1.05 ? (v outx + v botx ) f sw for channels 1 and 3 and l = 0.70 ? (v outx + v botx ) f sw for channel 2 figure 9. feedback resistor divider 8603 f09 swx lt8603 fbx c out r1 r2 c ff (optional) the value of input capacitance is a function of the source impedance. in general, the higher the source impedance, the higher the required input capacitance. the typical applications section provides reasonable starting values for input capacitance but careful evaluation of each appli - cation must be made to ensure adequate design margin. buck regula tors setting the output voltages the output voltages of the buck channels are set with a resistor divider from the output to the related fbx pin as shown in figure 9. the value of r2 is best selected first as this establishes how much current is in the string based on i = v fb /r2 where v fb = 1.0v for the high voltage channels and 0.8v for the low voltage channel. the current should be chosen such that it is not influenced by anticipated leakage or noise. r1 can then be calculated from: r1 = r2 ? v outx fb ref C 1 ? ? ? ? ? ? ? ? ? ? c ff can optionally be used to improve the transient response and stability of the internally compensated feed - back loops. the values shown in the typical applications section will provide a good starting point for selecting cff though careful evaluation of regulator stability should be made to ensure adequate design margin. buck: operating frequency and input voltage range each buck regulator s respective minimum on-time, t on(min) , and minimum off-time, t off(min) , impose lt8603 8603f
28 for more information www.linear.com/lt8603 applications information where v outx is the output voltage for the corresponding channel, v botx is the voltage across the bottom switch for the corresponding channel, f sw is the switching frequency in mhz, and l is in h. once the inductance is selected, the inductor current ripple and peak current can be calculated as: ?i lx = v outx lx ? f sw ? 1C v outx pv inx(max) ? ? ? ? ? ? ? ? ? ? i lx(peak) = i outx(max) + ?i lx 2 where pv inx(max) is the maximum input voltage for each channel in a given application and i outx(max) is the maxi- mum output current for each channel in a given applica - tion. to avoid overheating and poor efficiency, an induc - tor must be chosen with an rms current rating that is greater than the maximum expected output load of the application. in addition, the saturation current rating of the inductor must be higher than the load plus half the ripple current. finally, for best efficiency the inductor series resistance should be as small as possible, and the core material should be intended for the application switching frequency. the optimum inductor for a given application may differ from the one indicated by this design guide. careful evalu - ation of the application circuit should be completed with the chosen inductor to ensure adequate design margin. buck: shorted output protection if the bottom mosfet current exceeds the valley current limit at the start of a clock cycle, the top mosfet is kept off until the overcurrent situation clears. this prevents the buildup of inductor current during a shorted output condi - tion. further, during overload or short-circuit conditions, the lt8603 safely tolerates operation with a saturated inductor. buck: input capacitor selection step-down converters draw current from the input sup - ply in pulses with very fast rise and fall times. an input capacitor is required to reduce the resultant voltage ripple at the input and minimize emi. for this function,?a ceramic x7r or x5r bypass capacitor should be placed between each buck channel s pv in pin and ground. to be most effective, the input capacitor must have low impedance at the switching frequency and an adequate ripple current rating. the worst case ripple current occurs when v out is one- half pv in . under this condition, the ripple current is: i cin(rms) = i out 2 reasonable starting values for the input capacitor are: 4.7 f for channels 1 and 3 10 f for channel 2 a word of caution is in order regarding the use of ceramic capacitors at the input. a ceramic input capacitor can combine with stray inductance to form a resonant tank circuit back to the supply. if power is applied quickly (for example by plugging the circuit into a live power source), this tank can ring, as much as doubling the input volt- age. the solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor. for details see analog devices application note 88. buck: output capacitor selection the output capacitor performs two functions. first, it fil - ters the inductor current to generate an output with low voltage ripple. second, it stores energy to minimize droop and overshoot during transient loads. because the lt8603 buck converters are able to operate at a high frequency, minimal output capacitance is necessary. the internally compensated current mode control loops are stable with - out requiring a minimum series resistance (esr) in the output capacitor. therefore ceramic capacitors may be used and will result in very low output ripple. you can estimate output ripple with the following equa - tions as appropriate: v ripple = ?i l 8 ? f sw ? c out , for ceramic lt8603 8603f
29 for more information www.linear.com/lt8603 applications information v ripple = ?i l ? esr, for aluminum or tantalum where v ripple is the peak-to-peak output ripple, f sw is the switching frequency, ?i l is the peak-to-peak ripple current in the inductor, c out is the output capacitor value in f and esr is the output capacitor series resistance. the low esr and small size of ceramic capacitors make them the preferred type for lt8603 applications. however, not all ceramic capacitors are the same. many of the higher value capacitors use dielectrics with high tem - perature and voltage coefficients. in particular y5v and z5u types lose a large fraction of their capacitance with applied voltage and at temperature extremes. because loop stability, transient response ripple and emi depend on the value of the input and output capacitors it is best to use x5r (max 85c) or x7r (max 125c) capacitors depending on the operating temperature range. electrolytic capacitors are also an option. the esrs of most aluminum electrolytic capacitors are too large to deliver low output ripple. tantalum, as well as newer, lower esr organic electrolytic capacitors intended for power supply use are suitable. choose a capacitor with a low enough esr for the required output ripple. because the volume of the capacitor determines its esr, both the size and value will be larger than a ceramic capacitor that would give similar ripple performance. one benefit is that larger capacitance may give better transient response for large changes in load current. the typical applications section provides a reason - able starting point for output capacitor values. note, for applications that intend to operate near minimum on- time, larger output capacitance values may be required to minimize output voltage ripple. careful evaluation of each application must be made to ensure adequate design margin. buck: boost capacitor selection the high voltage channels require a voltage above pv in to drive the gates of the top nfet switches. connecting a capacitor between each channels bst and sw pins cre - ates this voltage with an approximate value of 3.3v. for most applications, a 0.1f ceramic capacitor is a good choice. buck: run, soft-start, tracking in addition to the global en/uvlo pin that controls the entire chip, each channel has its own independent control pin or pins. the low voltage channel has a run pin with a fixed inter - nal threshold of 1.2v. when the run pin exceeds 1.2v, a soft start is initiated which brings the low voltage channel into regulation in approximately 1.0ms. channel 1 and channel 2 have dual purpose trkssx control pins which can be used to ramp each output in a controlled way. each channel s feedback pin voltage will regulate to the lower of the corresponding trkss pin and the internal 1v reference. these pins can therefore provide output voltage tracking. in addition, there is an internal constant current pull-up of 2.4a at each trkss pin that can be used to charge an external capacitor to provide a programmable output soft-start function. the soft-start ramp time can be calculated from: t ss = c trkss ? 1v 2.4a the trkssx pin is pulled down through approximately 330?. it will be pulled down if temperature protection is activated. to achieve coincident tracking, connect a resistor divider from the controlling output to the trkss pin of the slave output. figure 10 shows the divider required for channel?2 to track v out1 . with this circuit, r1 and r2 values should be chosen to minimize the offset from the 2.4 a pull- up current. to achieve ratiometric tracking, connect both trkss1 and trks s2 to a single capacitor to ground. figure 10 shows the output waveforms for both coinci - dent and ratiometric tracking. note: pulling trkss1 and trkss2 to ground does not guarantee the respective channel will never display a switching cycle. lt8603 8603f
30 for more information www.linear.com/lt8603 applications information buck: burst mode operation with the sync pin held low to select burst mode opera - tion, the lt8603 will automatically transition to burst mode at light load for best efficiency. in burst mode operation, most of the circuits are shut down between switch-on bursts to minimize power loss. if at least one channel remains full frequency, the oscillator remains on and all bursts are synchronized to the appropriate phase of the oscillator. if all channels go into burst mode operation, the oscillator will also shut off between bursts with a further savings in power. because the channels of the lt8603 may have different loads, channels can have different switching frequencies when in burst mode operation. general functions general: power good comparators each lt8603 channel has a power good comparator with an open drain output pin, pgx. for the buck channels, each pg pin is pulled low when the corresponding feed - back voltage is either above or below its reference voltage by more than 8%. the boost channels pg pin is pulled low when its feedback voltage is below its reference volt - age by more than 8%. see the electrical characteristics table for more information on each channel s power good thresholds. note, the pg outputs are not valid until intv cc rises above 2.7v. general: power-on reset timer the lt8603 provides a programmable reset timer. the poren pin is the enable for the reset timer and includes a 1a internal pull-up. once enabled, the reset timer begins an internal clock counter that terminates after 64 cycles. upon counter termination, the rst open-drain pull-down releases allowing the pin to transition high. the rst out - put includes a weak, 100k , internal pull-up resistor to approximately 2v. the power-on reset timeout period, t rst , can be pro - grammed by connecting a capacitor, c por , between the cpor pin and ground. the value of t rst is calculated by: t rst = 35.2 ? c por where c por is in pf and t rst is in microseconds. for exam - ple, using a capacitor value of 8.2nf gives a 289ms reset timeout period. the accuracy of t rst will be determined figure 10. tracking output waveforms trkss2 v out1 r1 r2 lt8603 coincident tracking v out1 > v out2 r1 = r2 ? v out2 ? 1 ( ) time (10a) coincident tracking v out1 v out2 output voltage time 8603 f10 (10b) ratiometric tracking v out 1 v out 2 output voltage lt8603 8603f
31 for more information www.linear.com/lt8603 applications information by several factors including the accuracy and temperature coefficient of the capacitor cpor, parasitic capacitance on the cpor pin and board trace, and system noise. it is not recommended to use capacitor values greater than 10nf for best accuracy. figure?11 shows the power-on reset timing. general: sequencing the lt8603 provides flexibility in sequencing each chan - nel s output including a power-on reset timer. each chan - nel has a power good output (p g1 to p g4 ) and input control pin or pins (trks s1 , trkss2 , run3 , fsel4a, and fsel4b). the por has a control input (poren) and for each buck regulator, the current loop formed by the input capacitor has the highest di/dt and should be made as small as possible by placing the input capacitor close to the pv in pin and the adjacent gnd pin. when using a physically large input capacitor, the resulting loop may be larger than optimum. in this case using a small case/ value capacitor placed close to the pv in and gnd pins plus a larger capacitor further away is preferred. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board, and their connections made on that layer. the boost controller output loop, including the diode and output capacitor components, has the highest d i /d t . as a result, the loop involving the diode and output capacitor should be kept as small as possible. place a local, unbroken ground plane under the applica - tion circuit on the layer closest to the surface layer. the sw and bst nodes should be made as small as possible to minimize noise coupling to sensitive traces. minimize traces connecting to the rt and all fb pins and provide ground shielding as needed to minimize noise coupling to these sensitive nodes. the exposed pad on the bottom of the package must have a good electrical and thermal connection to the board ground. for best performance, maximize board ground planes and thermal vias under and near the part. figure 11. power-on reset timing 8601 f11 a reset output ( rst ). all 5 outputs are open-drain. a sequencing example is shown in figure 12. in this example, channel 4 starts first and soft-starts inter - nally. when channel 4 reaches regulation, channels?1 and 2 start up and ramp according to r1/c trkssx . once both v out1 and v out2 reach regulation, channel 3 starts. when out3 is in regulation, then the por timer is started. pcb layout for proper operation and minimum emi, care must be taken during printed circuit board layout. a recom - mended board layout is available with the latest lt8603 demo board. some general guidelines are available in the remainder of this section. figure 12. sequencing the outputs and por 8603 f12 r1 poren rst cpor fsel4b pg3 pg2 lt8603 pg1 run3 trkss2 trkss1 pg4 fsel4a intvcc r2 r3 r4 reset lt8603 8603f 1ms/div poren 1v/div cpor 1v/div rst 2v/div
32 for more information www.linear.com/lt8603 applications information the recommended layer use for a 4-layer board is: layer 1 (components): use 2oz (70m ) copper. unbroken high frequency/high current routing. (c in loop, sw node, bst node, inductor, c out ), high current dc routing, ground plane fill. layer 2 (internal): unbroken ground plane. layer 3 (internal) : signal routing, ground plane on remainder. layer 4 (bottom) : use 2oz ( 70m ) copper ; high cur - rent dc routing (pv in , v out ), ground plane on remainder. thermal considerations the exposed pad is the main path for conducting heat from the silicon die to the pc board and the surrounding air. thermal vias should be placed under the device to conduct heat down to internal ground planes and the back side of the board. multiple small vias work better than a few large ones as copper is a much better conductor than any solder which may or may not fill them. the planes will distribute heat over a larger area and thus reduce the thermal resistance from the package to the air. a good design can achieve an effective ja of 22 c /w. power dissipation within the lt8603 can be estimated by sum - ming the power dissipated in each channel. calculate each channel s power loss from an efficiency measurement and subtract external component losses such as induc- tors, power transistors, and diodes. the die temperature is calculated by multiplying the total lt8603 power dis - sipation by the thermal resistance from junction to die ja and adding the ambient temperature. the maximum load current should be derated as the ambient tempera - ture approaches the maximum junction rating. figure 13 shows the current derating factor to avoid exceeding the maximum junction temperature. the thermal derating curves of figure 13 are based on the front page application (ch 1 : 5v , ch?2 :?3.3v, ch 3 : 1.2v, ch4: 8v ). the currents decrease uniformly as a percent - age of maximum. although application dependent, this figure 13. thermal derating, e- and i-grade set of curves is representative of typical applications. final current derating should be based on temperature measurements in the final application and environment. the lt8603 will stop switching if the internal tempera - ture rises too high. this thermal protection is above the maximum reliable operating temperature and is intended as a failsafe only. lt8603 8603f 24v in , 2.2mhz ambient temperature (c) 0 25 50 75 100 125 0 20 3.5in x 3.5in 4?layer board 40 60 80 100 % of max load current (%) 8603 f13 2oz cu top and bottom limited by maximum junction temperature ja = 22c/w 12v in , 1mhz 12v in , 2.2mhz 24v in , 1mhz
33 for more information www.linear.com/lt8603 details of front page application typical applications start-up sequence l1 wurth 74437336033 l2 wurth 74437336015 l3 wurth 74437324010 l4 wurth 7443736015 sd1 pmeg060v050epd m1 rjk0651dpb-00 m2 fk3306010l l3 1.0h c9, 22pf r10, 187k r11, 374k c15 47f out3 1.2v c12 0.1f l2 1.5h c13, 15pf r8, 1meg r9, 432k c14 47f out2 3.3v r12 28.7k c10, 4.7f c11, 4.7f c8, 2.2nf c7, 2.2nf c2 100f m1 sd2* sd1 l4 1.5h r1 4m c1 4.7f cv in1 ** 4.7f cv in2 ** 4.7f v batt 2v to 20v transients to 42v (4.3v to start) c6 0.1f l1, 3.3h c8, 3.3pf r6, 1meg r7, 249k c5 22f out1 5.0v 8603 ta03a isp4 fb4 trkss1 trkss2 intv cc4 intv cc fsel4a run3 poren fsel4b sync cpor en/uvlo isn4 gate4 v in pv in1 pv in2 bst1 sw1 fb1 bst2 sw2 fb2 bias pv in3 sw3 fb3 pg1 pg2 pg3 pg4 rst lt8603 rt gnd *sd2 optionally provides reverse battery protection. replace with short if required. **cv in1 , cv in2 , and cv in3 should be placed as close as possible to their respective pv in pins. *** m2 is recommended for lowest quiescent current when channel 4 is inactive c16, 1000pf cv in3 ** 4.7f m2*** r4 1meg r5 110k boost on/off intv cc4 out4 8v for v bat t < 8.4v v bat t ? 0.4v for v bat t > 8.4 lt8603 8603f v in v out4 v out3 v out2 v out1 4ms/div 2v/div 8603 ta03b
34 for more information www.linear.com/lt8603 four regulated outputs with channel 4 configured as a sepic typical applications start-up sequence l1 wurth 74437336033 l2 wurth 74437336015 l3 wurth 74437324010 l4 wurth 74485540220 sd1 pmeg060v050epd m1 bsz067n06ls3 l3, 1.0h c15, 22pf r10, 499k r11, 1meg c16 47f 1.2v c12 0.1f l2, 1.5h c13, 15pf r8, 825k r9, 357k c14 47f 3.3v r12 28.7k c10, 4.7f c11, 4.7f c9, 2.2nf c7, 2.2nf l5 2.2h m1 sd2* sd1 sd4 sd3 l4 2.2h r1 4m c1 20f cv in1 ** 4.7f cv in2 ** 4.7f v batt 3v to 42v (4.3v to start) c6 0.1f l1, 3.3h c8, 3.3pf r6, 1meg r7, 249k c17 22f out1 5.0v 8603 ta04a isp4 fb4 trkss1 trkss2 intv cc4 intv cc fsel4a run3 fsel4b sync en/uvlo isn4 gate4 v in pv in1 pv in2 bst1 sw1 fb1 bst2 sw2 fb2 bias pv in3 sw3 fb3 lt8603 rt gnd *sd2 optionally provides reverse battery protection. replace with short if not required. sd3 ensure start-up. sd4 mainains v in at v batt < 4v. **cv in1 , cv in2 , and cv in3 should be placed as close as possible to their respective pv in pins. c2 20f c5 100f out4 r3 806k r2 1meg unused pins not shown: pg1-4, por, cpor, rst v out 4 = 0.8 ? (r4 + r5) r5 + r4 1meg r5 110k cv in3 ** 4.7f ? ? lt8603 8603f 8603 ta04b v out3 v out2 v out1 v out4 v in at 10v/div 20ms/div 2v/div 10v/div
35 for more information www.linear.com/lt8603 typical applications c6 0.1f l1, 2.2h c16, 10pf r12, 1meg r13, 665k c4 47f 2.5v l3, 1.0h c15, 22pf r6, 499k r9, 1meg c7 47f 1.2v c5 0.1f l2, 2.2h c14, 15pf r10, 825k r11, 357k c13 47f 3.3v r8 28.7k c10, 4.7f c11, 4.7f c9, 2.2nf c8, 2.2nf c3, 4.7f l4 5.6h r4 887k m1 sd1 c12 22f v batt 4v to 20v r1 887k 8603 ta05a trkss1 trkss2 intv cc4 intv cc pg2 run3 fsel4b fsel4a sync en/uvlo v in pv in1 pv in2 gate4 isn4 isp4 fb4 bst2 sw2 fb2 bias pv in3 sw3 fb3 lt8603 rt gnd out4 5v at 500ma r2, 422k bst1 sw1 fb1 r7 10k c2, 4.7f c1, 4.7f r3 40m r5, 169k unused pins not shown: pg1-4, por, cpor, rst four regulated outputs with channel 4 driven from channel 2 start-up sequence l1 wurth 74437324022 l2 wurth 74437324022 l3 wurth 74437321010 l4 wurth 74437324056 sd1 pmeg6030etp m1 rjk0651dpb-00 lt8603 8603f 8603 ta05b v out3 v out1 v out2 v out4 v in at 5v/div 10ms/div 2v/div 5v/div
36 for more information www.linear.com/lt8603 typical applications l3, 1.0h c15, 22pf r10, 499k r11, 1meg c7 47f out3 1.2v l2 1.5h c13, 15pf r8, 825k r9, 357k c14 47f out2 3.3v c6 0.1f c12 0.1f l1 2.2h c5, 3.3pf r6, 1meg r7, 249k c4 22f out1 5.0v r8 28.7k c10, 4.7f c11, 4.7f c9, 2.2nf c8, 2.2nf m1 sd1 c2 22f 4.7f v batt 6v to 16v 8603 ta06a trkss1 trkss2 intv cc4 intv cc run3 fsel4a fsel4b sync v in en/uvlo gate4 pg4 fb4 bst1 sw1 fb1 bias sw2 fb2 lt8603 rt gnd out4 48v at 200ma pv in3 sw3 fb3 unused pins not shown: pg1-4, por, cpor, rst bst2 r5 15.4k r4 909k f1 bel ? 0zcj0016ff2e isp4 isn4 pv in1 pv in2 r1 10m l4 22h r3 280k c1 r2 1meg c3 10pf + four regulated outputs with channel 4 providing 48v output start-up sequence l1 wurth 74437336022 l2 wurth 74437336015 l3 wurth 74437324010 l4 wurth 74437346220 sd1 pmeg060v05epd m1 buk9y58-75, 115 at 10v/div lt8603 8603f 5v/div 8603 ta06b v out4 v in v out1 v out2 v out3 at 5v/div at 2v/div at 2v/div at 2v/div 100ms/div 2v/div 10v/div
37 for more information www.linear.com/lt8603 package description please refer to http://www.linear.com/product/lt8603#packaging for the most recent package drawings. 6.00 0.10 (4 sides) note: 1. drawing is a jedec package outline variation of (wjjd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.45 or 0.35 45 chamfer 0.40 0.10 4039 1 2 bottom view?exposed pad 4.50 ref (4-sides) 4.42 0.10 4.42 0.10 4.42 0.05 4.42 0.05 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uj40) qfn rev ? 0406 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.50 0.05 (4 sides) 5.10 0.05 6.50 0.05 0.25 0.05 0.50 bsc package outline r = 0.10 typ uj package 40-lead plastic qfn (6mm 6mm) (reference ltc dwg # 05-08-1728 rev ?) information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. lt8603 8603f
38 for more information www.linear.com/lt8603 www.linear.com/lt8603 ? analog devices, inc. 2017 lt 1117 ? printed in usa related parts part number description comments lt8602 42v, quad output (2.5a+1.5a+1.5a+1.5a) 95% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q ?=?25a v in ?=?3v to?42v, v out(min) =?0.8v, i q ?=?25a, i sd ?LT8610 42v, 2.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q ?=?2.5a v in ?=?3.4v to?42v, v out(min) ?=?0.97v, i q ?=?2.5a, i sd ?LT8610a/8610ab 42v, 3.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q? =?2.5a v in ?=?3.4v?to?42v, v out(min) ?=?0.97v, i q ?=?2.5a, i sd ?LT8610ac 42v, 3.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q? =?2.5a v in ?=?3v?to?42v, v out(min) ?=?0.8v, i q ?=?2.5a, i sd ?

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